diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-07-27 23:11:27 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-07-27 23:11:27 +0000 |
| commit | 3dee17581c38ce598376e83666c54a6b5d96ef05 (patch) | |
| tree | 4ec737ab48ff7ec627efd68de9aab53e37e5a4c4 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | cef21c354408980eab7922c35af7523b08b5bec9 (diff) | |
Fix some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index ee794911d6..a21cf5b83e 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1656,9 +1656,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; case ISD::AND: - // FIXME: should add check in getImmediateForOpcode to return a value - // indicating the immediate is a run of set bits so we can emit a bitfield - // clear with RLWINM instead. switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) { default: assert(0 && "unhandled result code"); case 0: // No immediate @@ -1690,6 +1687,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Tmp3 = Tmp2 >> 16; // MB Tmp2 &= 0xFFFF; // ME + // FIXME: Catch SHL-AND in addition to SRL-AND in this block. if (N.getOperand(0).getOpcode() == ISD::SRL) if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { |