diff options
| author | Jim Laskey <jlaskey@mac.com> | 2005-08-12 23:38:02 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-08-12 23:38:02 +0000 |
| commit | 847c3a976bb225a1ce9efdd5d11b8ef292c01d9a (patch) | |
| tree | 2312025736f5c7b51aff186d1b090a8e6ed3ba41 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 7e03c749419da9989b2ae5607f072dcd73c16192 (diff) | |
1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
(~x)|y and x|(~y) yielding ORC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22771 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index cef895b5d2..500333fb29 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1717,10 +1717,17 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; } } + if (isOprNot(N.getOperand(1))) { + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); + BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } if (isOprNot(N.getOperand(0))) { - Tmp1 = SelectExpr(N.getOperand(0).getOperand(0)); - Tmp2 = SelectExpr(N.getOperand(1)); - BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1); + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); + BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2); RecordSuccess = false; return Result; } @@ -1737,6 +1744,20 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; if (SelectIntImmediateExpr(N, Result, PPC::ORIS, PPC::ORI)) return Result; + if (isOprNot(N.getOperand(1))) { + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); + BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } + if (isOprNot(N.getOperand(0))) { + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); + BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } // emit regular or Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); |