Do the right thing and enable 64 bit regs under the control of a subtarget

option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 8 deletions

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index d294f08fba..8cc538df83 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -94,19 +94,16 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
-    // 64 bit PowerPC implementations can support i64 types directly
-    // FIXME: enable this once it works.
-    //addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
     // They also have instructions for converting between i64 and fp.
     setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
     setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+  }
+
+  if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
+    // 64 bit PowerPC implementations can support i64 types directly
+    addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
     // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
     setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
-    // 32 bit PowerPC wants to expand i64 shifts itself.
-    // FIXME: remove these once we natively handle i64 shifts.
-    setOperationAction(ISD::SHL, MVT::i64, Custom);
-    setOperationAction(ISD::SRL, MVT::i64, Custom);
-    setOperationAction(ISD::SRA, MVT::i64, Custom);
   } else {
     // 32 bit PowerPC wants to expand i64 shifts itself.
     setOperationAction(ISD::SHL, MVT::i64, Custom);