diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-05-26 23:10:12 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-05-26 23:10:12 +0000 |
| commit | 6848be1a27e08a89dcd4dd69f746471a608012cd (patch) | |
| tree | 15b6ed90180222e37f9a37369300d5f5014e1bca /lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 8e7d056bc5c0688501f6721994c8f4074d699c69 (diff) | |
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index b33aeb8fbb..18e1cbacb4 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1160,7 +1160,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { abort(); case 1: return SDOperand(); // ret void is legal - case 2: { + case 3: { MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg; if (MVT::isVector(ArgVT)) @@ -1180,8 +1180,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { DAG.getMachineFunction().addLiveOut(ArgReg); break; } - case 3: - Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), + case 5: + Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), SDOperand()); Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); // If we haven't noted the R3+R4 are live out, do so now. |