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authorNate Begeman <natebegeman@mac.com>2004-08-13 04:45:14 +0000
committerNate Begeman <natebegeman@mac.com>2004-08-13 04:45:14 +0000
commit293d88ca8b776f6c8b0d36375458602cb2ae67d5 (patch)
tree5f458803935607b56212236bf77e9aa5f7de0685 /lib/Target/PowerPC/PPC32ISelSimple.cpp
parent8cfa427d9c5a95c96658c033e0f348ffd23920f5 (diff)
Fix 177.mesa compilation, don't use floating point regs for base addresses!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15720 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC32ISelSimple.cpp')
-rw-r--r--lib/Target/PowerPC/PPC32ISelSimple.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index f17515942d..eabe9d83ad 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1535,7 +1535,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
.addReg(PPC::R1);
if (GPR_remaining > 0) {
BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
- .addSImm(ArgOffset).addReg(ArgReg);
+ .addSImm(ArgOffset).addReg(PPC::R1);
CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
}
}