aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff options
context:
space:
mode:
authorNate Begeman <natebegeman@mac.com>2004-11-07 20:23:42 +0000
committerNate Begeman <natebegeman@mac.com>2004-11-07 20:23:42 +0000
commit075cdc655e2466d6b7e98f88d2fccec26223298c (patch)
tree0defa4324a8a2fa0c9f79346264352195eb743e4 /lib/Target/PowerPC/PPC32ISelSimple.cpp
parent18224032d3b26cad39991fc569948f15cf5ed953 (diff)
Disable bogus cast elimination when the cast is used by a setcc instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17583 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC32ISelSimple.cpp')
-rw-r--r--lib/Target/PowerPC/PPC32ISelSimple.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 5314dada04..1dd946a421 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -3163,15 +3163,15 @@ void PPC32ISel::visitCastInst(CastInst &CI) {
// emit them, as the store instruction will implicitly not store the zero or
// sign extended bytes.
if (SrcClass <= cInt && SrcClass >= DestClass) {
- bool AllUsesAreStoresOrSetCC = true;
+ bool AllUsesAreStores = true;
for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
- if (!isa<StoreInst>(*I) && !isa<SetCondInst>(*I)) {
- AllUsesAreStoresOrSetCC = false;
+ if (!isa<StoreInst>(*I)) {
+ AllUsesAreStores = false;
break;
}
// Turn this cast directly into a move instruction, which the register
// allocator will deal with.
- if (AllUsesAreStoresOrSetCC) {
+ if (AllUsesAreStores) {
unsigned SrcReg = getReg(Op, BB, MI);
BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
return;