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authorOwen Anderson <resistor@mac.com>2012-01-24 18:37:29 +0000
committerOwen Anderson <resistor@mac.com>2012-01-24 18:37:29 +0000
commit4f8dc7b17accf4f2ec953b80b2cc79786207492e (patch)
tree2edc4a99662a5d77bf89962cb3a1d76dbd1ade54 /lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
parente983a134e7e40e214f590c3d8ba565bb85f39628 (diff)
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp')
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 262f97c36a..5a6827ffd8 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -57,7 +57,7 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
- unsigned getBinaryCodeForInstr(const MCInst &MI,
+ uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {