erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 14 insertions, 14 deletions

diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
index a9c1d09613..4df2277979 100644
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
@@ -168,11 +168,11 @@ StoreInDirectAM (SDValue Op, SDValue N, SDValue &fsr)
     if (LD) {
       fsr = LD->getBasePtr();
     }
-    else if (isa<RegisterSDNode>(N.Val)) { 
+    else if (isa<RegisterSDNode>(N.getNode())) { 
       //FIXME an attempt to retrieve the register number
       //but does not work
       DOUT << "this is a register\n";
-      Reg = dyn_cast<RegisterSDNode>(N.Val);
+      Reg = dyn_cast<RegisterSDNode>(N.getNode());
       fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);  
     }
     else {
@@ -198,7 +198,7 @@ LoadFSR (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
     return true;
   }
   else if (N.getOpcode() == PIC16ISD::Package) {
-    CurDAG->setGraphColor(Op.Val, "blue");
+    CurDAG->setGraphColor(Op.getNode(), "blue");
     CurDAG->viewGraph();
   }
 
@@ -227,7 +227,7 @@ LoadNothing (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
 /// expanded, promoted and normal instructions.
 SDNode* PIC16DAGToDAGISel::Select(SDValue N) 
 {
-  SDNode *Node = N.Val;
+  SDNode *Node = N.getNode();
   unsigned Opcode = Node->getOpcode();
 
   // Dump information about the Node being selected
@@ -262,8 +262,8 @@ SDNode* PIC16DAGToDAGISel::Select(SDValue N)
 
 #ifndef NDEBUG
   DOUT << std::string(Indent-2, ' ') << "=> ";
-  if (ResNode == NULL || ResNode == N.Val)
-    DEBUG(N.Val->dump(CurDAG));
+  if (ResNode == NULL || ResNode == N.getNode())
+    DEBUG(N.getNode()->dump(CurDAG));
   else
     DEBUG(ResNode->dump(CurDAG));
   DOUT << "\n";
diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp
index f067747b1c..485b934142 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.cpp
+++ b/lib/Target/PIC16/PIC16ISelLowering.cpp
@@ -334,7 +334,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
   LoadSDNode *LD  = cast<LoadSDNode>(N);
   SDValue Ptr   = LD->getBasePtr();
   if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
-    if (ISD::isNON_TRUNCStore(Chain.Val)) {
+    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
       if (PrevST->getBasePtr() == Ptr &&
           PrevST->getValue().getValueType() == N->getValueType(0))
@@ -352,7 +352,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
   Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
   // FIXME: Add to worklist may not be needed. 
   // It is meant to merge sequences of add with constant into one. 
-  DCI.AddToWorklist(toWorklist.Val);   
+  DCI.AddToWorklist(toWorklist.getNode());   
   
   // Create the tokenfactors and carry it on to the build_pair node
   OutChains[0] = Outs[0].getValue(1);
@@ -443,7 +443,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
       changed = true;
       // LowerLOAD returns a Package node or it may combine and return 
       // anything else.
-      SDValue lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
+      SDValue lowered = LowerLOAD(InOp[i].getNode(), DAG, DCI);
 
       // So If LowerLOAD returns something other than Package, 
       // then just call ADD again.
@@ -462,7 +462,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
       changed = true;
       // Must call LowerADDSUB recursively here,
       // LowerADDSUB returns a Package node.
-      SDValue lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
+      SDValue lowered = LowerADDSUB(InOp[i].getNode(), DAG, DCI);
 
       LoOps[i] = lowered.getOperand(0);
       HiOps[i] = lowered.getOperand(1);
@@ -543,7 +543,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
   // FIXME: Just copy right now.
   ArgValues.push_back(Root);
 
-  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+  return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
                             ArgValues.size()).getValue(Op.getResNo());
 }
 
@@ -622,7 +622,7 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
       if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
           (Src.getOpcode() == ISD::SIGN_EXTEND) || 
           (Src.getOpcode() == ISD::ZERO_EXTEND)) {
-        Src = Src.Val->getOperand(0);
+        Src = Src.getNode()->getOperand(0);
         Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
         return Stores[0];
       }
@@ -721,10 +721,10 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
           // We want to merge sequence of add with constant to one add and a 
           // constant, so add the ADD node to worklist to have llvm do that 
           // automatically.
-          DCI.AddToWorklist(toWorkList.Val); 
+          DCI.AddToWorklist(toWorkList.getNode()); 
 
           // We don't need the Package so add to worklist so llvm deletes it
-          DCI.AddToWorklist(Src.Val);
+          DCI.AddToWorklist(Src.getNode());
           retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
         }