Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 58 insertions, 0 deletions

diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index ab1258a163..b6194390c8 100644
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -139,6 +139,10 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   case Mips::BteqzT8CmpX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
     break;
+  case Mips::BteqzT8CmpiX16:
+    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
+                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
+    break;
   case Mips::BteqzT8SltX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
     break;
@@ -150,6 +154,10 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   case Mips::BtnezT8CmpX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
     break;
+  case Mips::BtnezT8CmpiX16:
+    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
+                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
+    break;
   case Mips::BtnezT8SltX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
     break;
@@ -433,6 +441,24 @@ void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
   BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
 
 }
+
+void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
+  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
+  unsigned regX = I->getOperand(0).getReg();
+  int64_t imm = I->getOperand(1).getImm();
+  MachineBasicBlock *target = I->getOperand(2).getMBB();
+  unsigned CmpOpc;
+  if (isUInt<8>(imm))
+    CmpOpc = CmpiOpc;
+  else if (isUInt<16>(imm))
+    CmpOpc = CmpiXOpc;
+  else
+    llvm_unreachable("immediate field not usable");
+  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
+  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
+}
+
 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
   if (validSpImm8(Imm))
     return get(Mips::AddiuSpImm16);
diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h
index 2e2ba9b926..2699a1c39e 100644
--- a/lib/Target/Mips/Mips16InstrInfo.h
+++ b/lib/Target/Mips/Mips16InstrInfo.h
@@ -118,6 +118,11 @@ private:
   void ExpandFEXT_T8I816_ins(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator I,
                              unsigned BtOpc, unsigned CmpOpc) const;
+
+  void ExpandFEXT_T8I8I16_ins(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+    unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const;
+
 };
 
 }
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
index c7adce3a5b..1a5c30b57a 100644
--- a/lib/Target/Mips/Mips16InstrInfo.td
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -51,6 +51,15 @@ class FI816_SP_ins<bits<3> _func, string asmstr,
 //
 
 
+class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
+                     InstrItinClass itin>:
+  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+        !strconcat(asmstr, asmstr2), [], itin>;
+
+class FRI16_ins<bits<5> op, string asmstr,
+                InstrItinClass itin>:
+  FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+      
 class F2RI16_ins<bits<5> _op, string asmstr,
                      InstrItinClass itin>:
   FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
@@ -565,6 +574,24 @@ def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> {
   let Defs = [T8];
 }
 
+//
+// Format: CMPI rx, immediate MIPS16e
+// Purpose: Compare Immediate
+// To compare a constant with the contents of a GPR.
+//
+def CmpiRxImm16: FRI16_ins<0b01110, "cmpi", IIAlu> {
+  let Defs = [T8];
+}
+
+//
+// Format: CMPI rx, immediate MIPS16e
+// Purpose: Compare Immediate (Extended)
+// To compare a constant with the contents of a GPR.
+//
+def CmpiRxImmX16: FEXT_RI16_ins<0b01110, "cmpi", IIAlu> {
+  let Defs = [T8];
+}
+
 
 //
 // Format: DIV rx, ry MIPS16e