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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-02-28 03:18:43 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-02-28 03:18:43 +0000 |
| commit | 980a9992383cde8fdc62323f1d8c5790e68b0828 (patch) | |
| tree | 792386560d893438ba5d6e906774e7f74bf88ace /lib/Target/Mips/MipsInstrInfo.td | |
| parent | b75673b6e18da3937e4cbcd944b081bdc28a6cf5 (diff) | |
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151615 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 7b3308b582..dc60cf438e 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -752,6 +752,10 @@ def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>; // instructions 0 and 1 in the sequence above during MC lowering. // SETGP2 is emitted just before register allocation and converted to // instruction 2 just prior to post-RA scheduling. +// +// These pseudo instructions are needed to ensure no instructions are inserted +// before or between instructions 0 and 1, which is a limitation imposed by +// GNU linker. def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>; def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "", |