[mips] Remove single-precision floating point instructions from multiclasses

FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170053 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 6 deletions

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index c3c12c1fea..5c20a1e586 100644
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -317,18 +317,18 @@ class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
 }
 
 // FP unary instructions without patterns.
-class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
-           RegisterClass DstRC, RegisterClass SrcRC> :
+class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
+           RegisterClass SrcRC> :
   FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
-      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
+      !strconcat(opstr, "\t$fd, $fs"), []> {
   let ft = 0;
 }
 
 // FP unary instructions with patterns.
-class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
-            RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
+class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
+            RegisterClass SrcRC, SDNode OpNode> :
   FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
-      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
+      !strconcat(opstr, "\t$fd, $fs"),
       [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
   let ft = 0;
 }