diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-02 00:02:45 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-02 00:02:45 +0000 |
| commit | f66b7b1ff667bbcf9d71f540488b49b38bf72b1d (patch) | |
| tree | ea0b4a2d674249d4f6c32c33cb32795420876728 /lib/Target/Mips/MipsISelLowering.cpp | |
| parent | bed5b0db452f9f94facf260ca8667cf670c26c5c (diff) | |
Expand unaligned i16 loads/stores for the Mips backend.
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 6ea2692d6f..d0ea2185e0 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -292,7 +292,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { switch (SVT) { case MVT::i64: case MVT::i32: - case MVT::i16: return true; case MVT::f32: return Subtarget->hasMips32r2Or64(); |