diff options
| author | Reed Kotler <rkotler@mips.com> | 2012-10-28 23:08:07 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2012-10-28 23:08:07 +0000 |
| commit | 3a9f4568fbb974844afacd12ab9b62e8844fd8ad (patch) | |
| tree | 6857eb2f9c8da8ddca4cda2b21e7b97ce30f8e9d /lib/Target/Mips/Mips16InstrInfo.td | |
| parent | 0d91c0b519e0053931bf9502ebeaf44d397812f0 (diff) | |
Implement brind operator for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166903 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 79b4757ad5..d4d61550b4 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -250,6 +250,12 @@ class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), [], itin> ; + +class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, + string asmstr, InstrItinClass itin>: + FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), + !strconcat(asmstr, "\t $rx"), [], itin> ; + // // RRR-type instruction format // @@ -508,6 +514,13 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { let isTerminator=1; let isBarrier=1; } + +def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { + let isBranch = 1; + let isIndirectBranch = 1; + let isTerminator=1; + let isBarrier=1; +} // // Format: LB ry, offset(rx) MIPS16e // Purpose: Load Byte (Extended) @@ -991,6 +1004,12 @@ class UncondBranch16_pat<SDNode OpNode, Instruction I>: let Predicates = [RelocPIC, InMips16Mode]; } +// Indirect branch +def: Mips16Pat< + (brind CPU16Regs:$rs), + (JrcRx16 CPU16Regs:$rs)>; + + // Jump and Link (Call) let isCall=1, hasDelaySlot=1 in def JumpLinkReg16: |