llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 25 insertions, 25 deletions

diff --git a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
index 111749e778..e7ed64e5c8 100644
--- a/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
@@ -318,13 +318,13 @@ void IA64AsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
    case GlobalValue::PrivateLinkage:
     break;
    case GlobalValue::GhostLinkage:
-    LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!");
+    llvm_unreachable("GhostLinkage cannot appear in IA64AsmPrinter!");
    case GlobalValue::DLLImportLinkage:
-    LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+    llvm_unreachable("DLLImport linkage is not supported by this target!");
    case GlobalValue::DLLExportLinkage:
-    LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+    llvm_unreachable("DLLExport linkage is not supported by this target!");
    default:
-    LLVM_UNREACHABLE("Unknown linkage type!");
+    llvm_unreachable("Unknown linkage type!");
   }
 
   EmitAlignment(Align, GVar);
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index adb4c4b5fb..fc24241a6c 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -215,7 +215,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
     
     if(isFP) { // if this is an FP divide, we finish up here and exit early
       if(isModulus)
-        LLVM_UNREACHABLE("Sorry, try another FORTRAN compiler.");
+        llvm_unreachable("Sorry, try another FORTRAN compiler.");
  
       SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
 
@@ -406,7 +406,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
                                   APFloat(+1.0f) : APFloat(+1.0))) {
       V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
     } else
-      LLVM_UNREACHABLE("Unexpected FP constant!");
+      llvm_unreachable("Unexpected FP constant!");
     
     ReplaceUses(SDValue(N, 0), V);
     return 0;
@@ -468,7 +468,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
 #ifndef NDEBUG
       N->dump(CurDAG);
 #endif
-      LLVM_UNREACHABLE("Cannot load this type!");
+      llvm_unreachable("Cannot load this type!");
     case MVT::i1: { // this is a bool
       Opc = IA64::LD1; // first we load a byte, then compare for != 0
       if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
@@ -504,7 +504,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
     unsigned Opc;
     if (ISD::isNON_TRUNCStore(N)) {
       switch (N->getOperand(1).getValueType().getSimpleVT()) {
-      default: LLVM_UNREACHABLE("unknown type in store");
+      default: llvm_unreachable("unknown type in store");
       case MVT::i1: { // this is a bool
         Opc = IA64::ST1; // we store either 0 or 1 as a byte 
         // first load zero!
@@ -524,7 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
       }
     } else { // Truncating store
       switch(ST->getMemoryVT().getSimpleVT()) {
-      default: LLVM_UNREACHABLE("unknown type in truncstore");
+      default: llvm_unreachable("unknown type in truncstore");
       case MVT::i8:  Opc = IA64::ST1;  break;
       case MVT::i16: Opc = IA64::ST2;  break;
       case MVT::i32: Opc = IA64::ST4;  break;
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 8e675eba9a..587860c5b5 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
 
         switch (getValueType(I->getType()).getSimpleVT()) {
           default:
-            LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg."); 
+            llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg."); 
           case MVT::f32:
             // fixme? (well, will need to for weird FP structy stuff,
             // see intel ABI docs)
@@ -298,7 +298,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
   // Finally, inform the code generator which regs we return values in.
   // (see the ISD::RET: case in the instruction selector)
   switch (getValueType(F.getReturnType()).getSimpleVT()) {
-  default: LLVM_UNREACHABLE("i have no idea where to return this type!");
+  default: llvm_unreachable("i have no idea where to return this type!");
   case MVT::isVoid: break;
   case MVT::i1:
   case MVT::i8:
@@ -362,7 +362,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
       SDValue ValToStore(0, 0), ValToConvert(0, 0);
       unsigned ObjSize=8;
       switch (ObjectVT.getSimpleVT()) {
-      default: LLVM_UNREACHABLE("unexpected argument type!");
+      default: llvm_unreachable("unexpected argument type!");
       case MVT::i1:
       case MVT::i8:
       case MVT::i16:
@@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
   if (InFlag.getNode())
     CallOperands.push_back(InFlag);
   else
-    LLVM_UNREACHABLE("this should never happen!");
+    llvm_unreachable("this should never happen!");
 
   // to make way for a hack:
   Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
@@ -516,7 +516,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
   SDValue RetVal;
   if (RetTyVT != MVT::isVoid) {
     switch (RetTyVT.getSimpleVT()) {
-    default: LLVM_UNREACHABLE("Unknown value type to return!");
+    default: llvm_unreachable("Unknown value type to return!");
     case MVT::i1: { // bools are just like other integers (returned in r8)
       // we *could* fall through to the truncate below, but this saves a
       // few redundant predicate ops
@@ -573,15 +573,15 @@ SDValue IA64TargetLowering::
 LowerOperation(SDValue Op, SelectionDAG &DAG) {
   DebugLoc dl = Op.getDebugLoc();
   switch (Op.getOpcode()) {
-  default: LLVM_UNREACHABLE("Should not custom lower this!");
+  default: llvm_unreachable("Should not custom lower this!");
   case ISD::GlobalTLSAddress:
-    LLVM_UNREACHABLE("TLS not implemented for IA64.");
+    llvm_unreachable("TLS not implemented for IA64.");
   case ISD::RET: {
     SDValue AR_PFSVal, Copy;
     
     switch(Op.getNumOperands()) {
      default:
-      LLVM_UNREACHABLE("Do not know how to return this many arguments!");
+      llvm_unreachable("Do not know how to return this many arguments!");
     case 1: 
       AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
       AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, 
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 5f53d7d804..2a1411ae68 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -113,7 +113,7 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
       .addFrameIndex(FrameIdx)
       .addReg(IA64::r2);
   } else 
-    LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg"
+    llvm_unreachable("sorry, I don't know how to store this sort of reg"
                      "in the stack");
 }
 
@@ -130,7 +130,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
   } else if (RC == IA64::PRRegisterClass) {
     Opc = IA64::ST1;
   } else {
-    LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
+    llvm_unreachable("sorry, I don't know how to store this sort of reg");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -164,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
       .addReg(IA64::r2)
       .addReg(IA64::r0);
   } else {
-    LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg"
+    llvm_unreachable("sorry, I don't know how to load this sort of reg"
                      "from the stack");
   }
 }
@@ -181,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
   } else if (RC == IA64::PRRegisterClass) {
     Opc = IA64::LD1;
   } else {
-    LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg");
+    llvm_unreachable("sorry, I don't know how to load this sort of reg");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index a1a7574c84..6e3471dab3 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -293,7 +293,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
 }
 
 unsigned IA64RegisterInfo::getRARegister() const {
-  LLVM_UNREACHABLE("What is the return address register");
+  llvm_unreachable("What is the return address register");
   return 0;
 }
 
@@ -302,17 +302,17 @@ unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
 }
 
 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
-  LLVM_UNREACHABLE("What is the exception register");
+  llvm_unreachable("What is the exception register");
   return 0;
 }
 
 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
-  LLVM_UNREACHABLE("What is the exception handler register");
+  llvm_unreachable("What is the exception handler register");
   return 0;
 }
 
 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
-  LLVM_UNREACHABLE("What is the dwarf register number");
+  llvm_unreachable("What is the dwarf register number");
   return -1;
 }