diff options
author | Bill Wendling <isanbard@gmail.com> | 2012-05-01 08:28:53 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2012-05-01 08:28:53 +0000 |
commit | 1fb5af610fbbf5740d8176d2d9b57fb4f95321e3 (patch) | |
tree | 09b65ca73b29a1f86f1013b00016c30307d2d65d /lib/Target/Hexagon/HexagonTargetMachine.cpp | |
parent | 4c2b0d446b655d9244df2bc05632c54561cda4a4 (diff) |
Merging r155902:
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r155902 | void | 2012-05-01 01:27:43 -0700 (Tue, 01 May 2012) | 7 lines
Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_31@155903 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonTargetMachine.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonTargetMachine.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index b9e6894936..55bbba7251 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -100,23 +100,23 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { } bool HexagonPassConfig::addInstSelector() { - PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine())); - PM.add(createHexagonISelDag(getHexagonTargetMachine())); - PM.add(createHexagonPeephole()); + PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine())); + PM->add(createHexagonISelDag(getHexagonTargetMachine())); + PM->add(createHexagonPeephole()); return false; } bool HexagonPassConfig::addPreRegAlloc() { if (!DisableHardwareLoops) { - PM.add(createHexagonHardwareLoops()); + PM->add(createHexagonHardwareLoops()); } return false; } bool HexagonPassConfig::addPostRegAlloc() { - PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine())); + PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine())); return true; } @@ -129,14 +129,14 @@ bool HexagonPassConfig::addPreSched2() { bool HexagonPassConfig::addPreEmitPass() { if (!DisableHardwareLoops) { - PM.add(createHexagonFixupHwLoops()); + PM->add(createHexagonFixupHwLoops()); } // Expand Spill code for predicate registers. - PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine())); + PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine())); // Split up TFRcondsets into conditional transfers. - PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine())); + PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine())); return false; } |