diff options
| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:40 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:40 +0000 |
| commit | fc992996f751e0941951b6d08d8f1e80ebec1385 (patch) | |
| tree | 9205e39624f5c786dee5160b882d65c7865e45b2 /lib/Target/Hexagon/HexagonSubtarget.cpp | |
| parent | 4eb4e5eb224b3d737558bcda8a0a369cc9d800e6 (diff) | |
misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonSubtarget.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonSubtarget.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 8744b7b32c..ce81a78bf9 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -61,9 +61,6 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); - // Max issue per cycle == bundle width. - InstrItins.IssueWidth = 4; - if (EnableMemOps) UseMemOps = true; else |