diff options
author | Andrew Trick <atrick@apple.com> | 2012-02-01 22:13:57 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-02-01 22:13:57 +0000 |
commit | ee498d3254b86bceb4f441741e9f442990647ce6 (patch) | |
tree | f2319c428f9e572162a0ca172a573da5ea39bcdf /lib/Target/Hexagon/HexagonSubtarget.cpp | |
parent | f18a9a2314542ad3b7a601b86969073519e19b0d (diff) |
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonSubtarget.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonSubtarget.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 83fb498f21..39c70223f9 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -52,6 +52,9 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); + // Max issue per cycle == bundle width. + InstrItins.IssueWidth = 4; + if (EnableMemOps) UseMemOps = true; else |