diff options
| author | Sirish Pande <spande@codeaurora.org> | 2012-05-03 21:52:53 +0000 |
|---|---|---|
| committer | Sirish Pande <spande@codeaurora.org> | 2012-05-03 21:52:53 +0000 |
| commit | 26f61a158b3cce69252c05cc0e79f500d6c3d92e (patch) | |
| tree | b3324a781f77ce12e2e208bff093187bb293e00e /lib/Target/Hexagon/HexagonMCInstLower.cpp | |
| parent | ff9229ecf09c1909adafcdd58134d3ac1414b565 (diff) | |
Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonMCInstLower.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonMCInstLower.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp index fbb331bdd8..70bddcc76a 100644 --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -49,7 +49,7 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI, switch (MO.getType()) { default: MI->dump(); - assert(0 && "unknown operand type"); + llvm_unreachable("unknown operand type"); case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; |