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| author | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:20 +0000 |
|---|---|---|
| committer | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:20 +0000 |
| commit | 0dac3919e52e28308deba555bbcb6286674d5495 (patch) | |
| tree | e282036a59d3425345998090955e7eae538cb5f5 /lib/Target/Hexagon/HexagonMCInstLower.cpp | |
| parent | 9f6852dcc292882845876ecc1181710a5c35fb1f (diff) | |
Support for Hexagon VLIW Packetizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155365 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonMCInstLower.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonMCInstLower.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp index fbb331bdd8..70bddcc76a 100644 --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -49,7 +49,7 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI, switch (MO.getType()) { default: MI->dump(); - assert(0 && "unknown operand type"); + llvm_unreachable("unknown operand type"); case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; |