diff options
| author | Wesley Peck <peckw@wesleypeck.com> | 2010-11-23 03:31:01 +0000 |
|---|---|---|
| committer | Wesley Peck <peckw@wesleypeck.com> | 2010-11-23 03:31:01 +0000 |
| commit | bf17cfa3f904e488e898ac2e3af706fd1a892f08 (patch) | |
| tree | f48d5532ddc3b52d2b73c4d8e1c4d78d8f59707f /lib/Target/Alpha | |
| parent | 5400570097a25f05694d451afed7f949281b789e (diff) | |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 9ae06eab75..e266eda743 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -125,7 +125,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) setOperationAction(ISD::SETCC, MVT::f32, Promote); - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote); + setOperationAction(ISD::BITCAST, MVT::f32, Promote); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); @@ -616,7 +616,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, "Unhandled SINT_TO_FP type in custom expander!"); SDValue LD; bool isDouble = Op.getValueType() == MVT::f64; - LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0)); + LD = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl, isDouble?MVT::f64:MVT::f32, LD); return FP; @@ -630,7 +630,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src); + return DAG.getNode(ISD::BITCAST, dl, MVT::i64, src); } case ISD::ConstantPool: { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); @@ -648,11 +648,11 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); const GlobalValue *GV = GSDN->getGlobal(); - SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i64, + SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i64, GSDN->getOffset()); // FIXME there isn't really any debug info here - // if (!GV->hasWeakLinkage() && !GV->isDeclaration() + // if (!GV->hasWeakLinkage() && !GV->isDeclaration() // && !GV->hasLinkOnceLinkage()) { if (GV->hasLocalLinkage()) { SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA, @@ -727,7 +727,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, MachinePointerInfo(SrcS), false, false, 0); - SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, + SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, MachinePointerInfo(DestS), false, false, 0); SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP, @@ -779,7 +779,7 @@ void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, SDValue Chain, DataPtr; LowerVAARG(N, Chain, DataPtr, DAG); - SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, + SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, MachinePointerInfo(), false, false, 0); Results.push_back(Res); |