diff options
author | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-20 00:28:31 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-20 00:28:31 +0000 |
commit | 4907d22a903357b19d67b45616d0cd249cb7049f (patch) | |
tree | 49025bc5743dede0e6388546467b58a5c4229fcd /lib/Target/Alpha/AlphaTargetMachine.cpp | |
parent | 9811ea456746684336db7d83b2976ad5130ab4d0 (diff) |
ret 0; works, not much else
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaTargetMachine.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaTargetMachine.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 8f26329405..37f71b25af 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -32,6 +32,9 @@ namespace llvm { cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha", cl::desc("Enable LSR for Alpha (beta option!)"), cl::Hidden); + cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha", + cl::desc("Enable DAG ISEL for Alpha (beta option!)"), + cl::Hidden); } unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) { @@ -94,7 +97,10 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - PM.add(createAlphaPatternInstructionSelector(*this)); + if (EnableAlphaDAG) + PM.add(createAlphaISelDag(*this)); + else + PM.add(createAlphaPatternInstructionSelector(*this)); if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(&std::cerr)); |