diff options
author | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-21 23:13:11 +0000 |
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committer | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-21 23:13:11 +0000 |
commit | 4633f1cde84b1dbb05dfbdce17ca6b483596cee7 (patch) | |
tree | 39dbb60444ff37cd07b4244090f8a17be3ef8bab /lib/Target/Alpha/AlphaTargetMachine.cpp | |
parent | f976c856fcc5055f3fc7d9f070d72c2d027c1d9d (diff) |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21424 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaTargetMachine.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaTargetMachine.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 7bc4852105..83e95a7cb3 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -1,12 +1,12 @@ //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // //===----------------------------------------------------------------------===// @@ -27,8 +27,8 @@ namespace { } namespace llvm { - cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha", - cl::desc("Enable LSR for Alpha (beta option!)"), + cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha", + cl::desc("Enable LSR for Alpha (beta option!)"), cl::Hidden); } @@ -50,7 +50,7 @@ unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) { } AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) - : TargetMachine("alpha", IL, true), + : TargetMachine("alpha", IL, true), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these {} @@ -59,7 +59,7 @@ AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) /// bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) { - + if (EnableAlphaLSR) { PM.add(createLoopStrengthReducePass()); PM.add(createCFGSimplificationPass()); @@ -88,12 +88,12 @@ bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, PM.add(createMachineFunctionPrinterPass(&std::cerr)); PM.add(createPrologEpilogCodeInserter()); - + // Must run branch selection immediately preceding the asm printer //PM.add(createAlphaBranchSelectionPass()); - + PM.add(createAlphaCodePrinterPass(Out, *this)); - + PM.add(createMachineCodeDeleter()); return false; } |