diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-13 23:36:35 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-13 23:36:35 +0000 |
| commit | 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 (patch) | |
| tree | 459ce71956b931173c43b156295d14e18f4748fc /lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | d7de496b23fca8145f777a56281457bf64e8bbad (diff) | |
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index cc6c108420..6be5e074a3 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -51,8 +51,9 @@ static long getLower16(long l) return l - h * IMM_MULT; } -AlphaRegisterInfo::AlphaRegisterInfo() - : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP) +AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) + : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + TII(tii) { } @@ -114,13 +115,13 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned InReg = MI->getOperand(1).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) + return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move unsigned OutReg = MI->getOperand(0).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex) + return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } } @@ -205,11 +206,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -266,7 +267,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) + MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { |