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| author | Evan Cheng <evan.cheng@apple.com> | 2007-04-25 07:12:14 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-04-25 07:12:14 +0000 |
| commit | 1e341729dd003ca33ecea4abf13134f20062c5f8 (patch) | |
| tree | 4bc71a3892c29b85687c6c6d46531aced64c4e01 /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 79b3bd395dc3303cde65e18e0524ed2f70268c99 (diff) | |
Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 71bf5b0e96..04b08b58bf 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -33,7 +33,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, oc == Alpha::CPYSTs) { // or r1, r2, r2 // cpys(s|t) r1 r2 r2 - assert(MI.getNumOperands() == 3 && + assert(MI.getNumOperands() >= 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && MI.getOperand(2).isRegister() && |