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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-09-04 06:12:19 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-09-04 06:12:19 +0000 |
| commit | f71df33671d7db53f6b1d1a6cb2e4d0062076a3b (patch) | |
| tree | 58f9a307de1ab93f4daf275d8529f05077f471fe /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | e147ceb2fa377edb14c7977f16c92e2815ff25aa (diff) | |
revert part of the last change, should fix regressions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23241 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 2af3e9b306..cc0392bdde 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1733,6 +1733,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2); return Result; } + + case ISD::AssertSext: + case ISD::AssertZext: + return SelectExpr(N.getOperand(0)); + } return 0; |