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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 19:52:25 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 19:52:25 +0000 |
| commit | c2c64fd3c632df179269db9c80b2d7f071115d2c (patch) | |
| tree | 9d338e5cf189a65f073491c5fa74254488725018 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | f6947c1bb84f1cd077987fe57f6c33f8319168e7 (diff) | |
Fix a bunch more alpha regressions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24304 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 791fcedccd..3218f03d63 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1533,7 +1533,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { N.getOperand(0).getValueType() == MVT::f32 && "only f32 to f64 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1); return Result; case ISD::ConstantFP: |