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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:08:46 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:08:46 +0000 |
| commit | b921f1b731ffff11d130d561a8880e216e4ace78 (patch) | |
| tree | 581180a3942c8438543f5fe5bed5225220d37a8f /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 2729e614fa85347483d2f3ab209ebbc9a4e88bcd (diff) | |
fix yet more regressions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24308 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index ec3479d15f..1127f8b9e4 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1530,7 +1530,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { N.getOperand(0).getValueType() == MVT::f64 && "only f64 to f32 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1); return Result; case ISD::FP_EXTEND: |