diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-10 16:59:55 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-10 16:59:55 +0000 |
| commit | 7b441dc966804e363a76db00cb238af6d93d8409 (patch) | |
| tree | d7f75b740dad141073d2311ec0e576480c01a326 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 105b2f5374d970822d6f33f7ec5d2ed1e9ef9c29 (diff) | |
fix a bunch of regressions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24269 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 96684baaf8..eb13486c7f 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1295,11 +1295,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { if (SrcType == MVT::f32) { Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1); Tmp1 = Tmp2; } Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1); MoveFP2Int(Tmp2, Result, true); return Result; |