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authorAndrew Lenharth <andrewl@lenharth.org>2005-08-01 17:47:28 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-08-01 17:47:28 +0000
commit01c8f6e452b16346defb09e94d1c928118498ee2 (patch)
tree7c0bffd95cb693a000a16ddbbbcf89238cf944de /lib/Target/Alpha/AlphaISelPattern.cpp
parent2b3b89c28e90ba9637614a398dc0eb743370a1c9 (diff)
use llabs not abs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22569 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 1af8aa6841..2697544cf2 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -678,7 +678,7 @@ static struct ms magic(int64_t d) {
const uint64_t two63 = 9223372036854775808ULL; // 2^63
struct ms mag;
- ad = abs(d);
+ ad = llabs(d);
t = two63 + ((uint64_t)d >> 63);
anc = t - 1 - t%ad; // absolute value of nc
p = 63; // initialize p
@@ -1847,9 +1847,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
//check if we can convert into a shift!
if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
(int64_t)CSD->getSignExtended() != 0 &&
- ExactLog2(abs((int64_t)CSD->getSignExtended())) != 0)
+ ExactLog2(llabs(CSD->getSignExtended())) != 0)
{
- unsigned k = ExactLog2(abs(CSD->getSignExtended()));
+ unsigned k = ExactLog2(llabs(CSD->getSignExtended()));
Tmp1 = SelectExpr(N.getOperand(0));
if (k == 1)
Tmp2 = Tmp1;