Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff

like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21270 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 21 deletions

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 1e8e38539f..9b07ff77a8 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1562,27 +1562,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
       }
       return Result;
     }
-  case ISD::ZERO_EXTEND_INREG:
-    {
-      Tmp1 = SelectExpr(N.getOperand(0));
-      MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
-      //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
-      switch(MVN->getExtraValueType())
-      {
-      default:
-        Node->dump();
-        assert(0 && "Zero Extend InReg not there yet");
-        break;
-      case MVT::i32: Tmp2 = 0xf0; break;
-      case MVT::i16: Tmp2 = 0xfc; break;
-      case MVT::i8: Tmp2 = 0xfe; break;
-      case MVT::i1: //handle this one special
-        BuildMI(BB, Alpha::ANDi, 2, Result).addReg(Tmp1).addImm(1);
-        return Result;
-      }
-      BuildMI(BB, Alpha::ZAPi, 2, Result).addReg(Tmp1).addImm(Tmp2);
-      return Result;
-    }
     
   case ISD::SETCC:
     {