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| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-20 06:59:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-20 06:59:32 +0000 |
| commit | f6fe9579505be86420beea04f2c9ecb0fd7c55fd (patch) | |
| tree | 856f7c6fb7784a907848f401ba68154c7e081dd7 /lib/Target/ARM/README-Thumb.txt | |
| parent | 401e10c4fbfcdcfade5065093e2ca97f69a1d144 (diff) | |
Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/README-Thumb.txt')
| -rw-r--r-- | lib/Target/ARM/README-Thumb.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/README-Thumb.txt b/lib/Target/ARM/README-Thumb.txt index cc017945d8..df94312d5f 100644 --- a/lib/Target/ARM/README-Thumb.txt +++ b/lib/Target/ARM/README-Thumb.txt @@ -244,3 +244,7 @@ to toggle the 's' bit since they do not set CPSR when they are inside IT blocks. Make use of hi register variants of cmp: tCMPhir / tCMPZhir. //===---------------------------------------------------------------------===// + +Thumb1 immediate field sometimes keep pre-scaled values. See +Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and +Thumb2. |