diff options
author | Evan Cheng <evan.cheng@apple.com> | 2007-01-19 07:51:42 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-01-19 07:51:42 +0000 |
commit | a8e2989ece6dc46df59b0768184028257f913843 (patch) | |
tree | c0e782730e267b35f0d15668d0689e6c322fe246 /lib/Target/ARM/README-Thumb.txt | |
parent | bd92d81d22c90433e968077aa0a4157d631d6365 (diff) |
ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/README-Thumb.txt')
-rw-r--r-- | lib/Target/ARM/README-Thumb.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/ARM/README-Thumb.txt b/lib/Target/ARM/README-Thumb.txt new file mode 100644 index 0000000000..e9e943d0ae --- /dev/null +++ b/lib/Target/ARM/README-Thumb.txt @@ -0,0 +1,17 @@ +//===---------------------------------------------------------------------===// +// Random ideas for the ARM backend (Thumb specific). +//===---------------------------------------------------------------------===// + +* Add support for compiling functions in both ARM and Thumb mode, then taking + the smallest. +* Add support for compiling individual basic blocks in thumb mode, when in a + larger ARM function. This can be used for presumed cold code, like paths + to abort (failure path of asserts), EH handling code, etc. + +* Thumb doesn't have normal pre/post increment addressing modes, but you can + load/store 32-bit integers with pre/postinc by using load/store multiple + instrs with a single register. + +* Make better use of high registers r8, r10, r11, r12 (ip). Some variants of add + and cmp instructions can use high registers. Also, we can use them as + temporaries to spill values into. |