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authorJohnny Chen <johnny.chen@apple.com>2011-03-24 21:36:56 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-03-24 21:36:56 +0000
commit9091bf25d97b8b43bd26ea03976d1f320c770a92 (patch)
treeb6124afa1500a68a2fb355df2de2ff2315f22954 /lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
parent83ccbff84fd38d8680ae39b3b629aee339478855 (diff)
T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h')
-rw-r--r--lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index b9cafeb831..f9d2bd0d38 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1140,7 +1140,7 @@ static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
&& "Unexpected opcode");
- assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
+ assert(NumOps >= 4 && "Thumb2 LdStMul expects NumOps >= 4");
NumOpsAdded = 0;