diff options
author | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 17:03:12 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 17:03:12 +0000 |
commit | f14d5cf33a0414637a874ef9a4cbc8e0cf1debee (patch) | |
tree | 3a8446a5b2be20b74ea5d73e601658a8a0fc52a1 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
parent | 067e2e2adb0c1e857b0ff5c25403a7585d7f9fad (diff) |
Also need to handle invalid imod values for CPS2p.
rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
-rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index b839a02d6a..ff19a385cf 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2965,8 +2965,10 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // opcodes which match the same real instruction. This is needed since there's // no current handling of optional arguments. Fix here when a better handling // of optional arguments is implemented. - if (Opcode == ARM::CPS3p) { - // Let's reject impossible imod values by returning false. + if (Opcode == ARM::CPS3p) { // M = 1 + // Let's reject these impossible imod values by returning false: + // 1. (imod=0b01) + // // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an // invalid combination, so we just check for imod=0b00 here. if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1) @@ -2977,13 +2979,18 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, NumOpsAdded = 3; return true; } - if (Opcode == ARM::CPS2p) { + if (Opcode == ARM::CPS2p) { // mode = 0, M = 0 + // Let's reject these impossible imod values by returning false: + // 1. (imod=0b00,M=0) + // 2. (imod=0b01) + if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1) + return false; MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags NumOpsAdded = 2; return true; } - if (Opcode == ARM::CPS1p) { + if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode NumOpsAdded = 1; return true; |