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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 20:21:38 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 20:21:38 +0000 |
| commit | ec30f6f5e5e53f384f3cbdade08ba654ef3680c7 (patch) | |
| tree | 4d5c524d79d9248065d099488d9240e545a4d281 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | ce1498bdbe32d0d6ab14d449d559ee76c0b30d9d (diff) | |
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index c28f7e12ef..884a056ef5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1106,6 +1106,14 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn, MI.addOperand(MCOperand::CreateImm(Offset)); OpIdx += 1; } else { + // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of + // A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1, + // we should reject this insn as invalid. + // + // Ditto for LDRBT. + if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1)) + return false; + // Disassemble the offset reg (Rm), shift type, and immediate shift length. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); |