diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 01:05:52 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 01:05:52 +0000 |
| commit | 8424a60fc9059d4ba7c45c80d28d86e3186fcf4e (patch) | |
| tree | 7da8c9a6c6e288e784225dfb32f4c788855ce966 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | 2c69f8eec6a51114799e3e80fa4903c5e3fc429c (diff) | |
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index fd4948552e..48a748b8ca 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -536,7 +536,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { return false; case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: - case ARM::SMMLA: case ARM::SMMLS: + case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8: if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; @@ -545,6 +545,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { case ARM::SMUAD: case ARM::SMUADX: // A8.6.167 SMLAD & A8.6.172 SMLSD case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX: + case ARM::USAD8: if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; @@ -562,12 +563,13 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { // Multiply Instructions. // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, -// SMLAD, SMLADX, SMLSD, SMLSDX: +// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is // only for {d, n, m}. // -// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX: +// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX, +// USAD8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} // // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, |