diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-10-21 20:02:19 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-10-21 20:02:19 +0000 |
| commit | cdcfa280568d5d48ebeba2dcfc87915105e090d1 (patch) | |
| tree | ae92cbccaac401ba652b1ca4f2ce3c2fb5f19854 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | a48aab924d93be3cdb4a230a9158d210b97b3f56 (diff) | |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index d077d46689..361cf91f01 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1959,14 +1959,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, // Second output register switch (Inst.getOpcode()) { - case ARM::VLD1d8T: - case ARM::VLD1d16T: - case ARM::VLD1d32T: - case ARM::VLD1d64T: - case ARM::VLD1d8T_UPD: - case ARM::VLD1d16T_UPD: - case ARM::VLD1d32T_UPD: - case ARM::VLD1d64T_UPD: case ARM::VLD1d8Q: case ARM::VLD1d16Q: case ARM::VLD1d32Q: @@ -2028,14 +2020,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, // Third output register switch(Inst.getOpcode()) { - case ARM::VLD1d8T: - case ARM::VLD1d16T: - case ARM::VLD1d32T: - case ARM::VLD1d64T: - case ARM::VLD1d8T_UPD: - case ARM::VLD1d16T_UPD: - case ARM::VLD1d32T_UPD: - case ARM::VLD1d64T_UPD: case ARM::VLD1d8Q: case ARM::VLD1d16Q: case ARM::VLD1d32Q: |