Emit the warning about the register list not being in ascending order only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 5 deletions

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 12225b00ed..dc5a417059 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -512,24 +512,27 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
   SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
     RI = Registers.begin(), RE = Registers.end();
 
-  unsigned HighRegNum = RI->first;
   DenseMap<unsigned, bool> RegMap;
   RegMap[RI->first] = true;
 
+  unsigned HighRegNum = RI->first;
+  bool EmittedWarning = false;
+
   for (++RI; RI != RE; ++RI) {
     const std::pair<unsigned, SMLoc> &RegInfo = *RI;
+    unsigned Reg = RegInfo.first;
 
-    if (RegMap[RegInfo.first]) {
+    if (RegMap[Reg]) {
       Error(RegInfo.second, "register duplicated in register list");
       return 0;
     }
 
-    if (RegInfo.first < HighRegNum)
+    if (!EmittedWarning && Reg < HighRegNum)
       Warning(RegInfo.second,
               "register not in ascending order in register list");
 
-    RegMap[RegInfo.first] = true;
-    HighRegNum = std::max(RegInfo.first, HighRegNum);
+    RegMap[Reg] = true;
+    HighRegNum = std::max(Reg, HighRegNum);
   }
 
   return ARMOperand::CreateRegList(Registers, S, E);