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| author | Jim Grosbach <grosbach@apple.com> | 2011-09-19 22:21:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-09-19 22:21:13 +0000 |
| commit | 7f739bee261debdf56bd89ac922b57eca53e91dc (patch) | |
| tree | fe5281737d5a141000592658edc67fe7e5512ac3 /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 463158fdb89001d398520cfc1cbb5f1384623dd8 (diff) | |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 46b0589cc5..ce3f747f2f 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -687,6 +687,18 @@ public: return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || Val == INT32_MIN; } + bool isMemTBB() const { + if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || + Mem.ShiftType != ARM_AM::no_shift) + return false; + return true; + } + bool isMemTBH() const { + if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || + Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1) + return false; + return true; + } bool isMemRegOffset() const { if (Kind != Memory || !Mem.OffsetRegNum) return false; @@ -1205,6 +1217,18 @@ public: Inst.addOperand(MCOperand::CreateImm(Val)); } + void addMemTBBOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); + Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); + } + + void addMemTBHOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); + Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); + } + void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, |