diff options
author | Owen Anderson <resistor@mac.com> | 2010-10-21 03:11:16 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2010-10-21 03:11:16 +0000 |
commit | d9707e3d852622197133a73dcb788a7fcd364015 (patch) | |
tree | faca0499ec6e582d1aa18f7c43292fa665669f48 /lib/Target/ARM/ARMScheduleA9.td | |
parent | 13a949071ce2c887ae81db9f6880a660ff33a76d (diff) |
Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 548bc7cd60..c22367716c 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1]>, + [1, 1]>, // // Double-precision to Integer Move InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1, 1]>, + [1, 1, 1]>, // // Single-precision FP Load InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1]>, + [2, 1]>, // // Integer to Double-precision Move InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1, 1]>, + [2, 1, 1]>, // // Single-precision to Integer Move InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, |