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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-01 20:50:58 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-01 20:50:58 +0000 |
| commit | cae6a12a999ef9434f110950d453814ab41d2156 (patch) | |
| tree | c1f3cf1a47464947a37ea9c0aef5424b5b6e0cb0 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | 45547b844d6a1cd69d6f71ec304948896c89bf43 (diff) | |
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 02058618ad..8acc172668 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -801,6 +801,14 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_Pipe1]>, InstrStage<4, [A9_MUX0, A9_NPipe]>], [9, 3, 2, 1]>, + + // + // Move + InstrItinData<IIC_VMOV, [InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<1, [A9_DRegsVFP], 0, Reserved>, + InstrStage<1, [A9_Pipe1]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1,1]>, // // Move Immediate InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_DRegsN], 0, Required>, @@ -819,14 +827,12 @@ def CortexA9Itineraries : ProcessorItineraries< [2, 1]>, // // Quad-register Permute Move - // Result written in N2, but that is relative to the last cycle of multicycle, - // so we use 3 for those cases InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_DRegsN], 0, Required>, // FIXME: all latencies are arbitrary, no information is available - InstrStage<4, [A9_DRegsVFP], 0, Reserved>, + InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_Pipe1]>, - InstrStage<2, [A9_MUX0, A9_NPipe]>], - [3, 1]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [2, 1]>, // // Integer to Single-precision Move InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_DRegsN], 0, Required>, @@ -869,6 +875,14 @@ def CortexA9Itineraries : ProcessorItineraries< [3, 1, 1]>, // + // Vector narrow move + InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_DRegsN], 0, Required>, + // Extra latency cycles since wbck is 6 cycles + InstrStage<7, [A9_DRegsVFP], 0, Reserved>, + InstrStage<1, [A9_Pipe1]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [3, 1]>, + // // Double-register FP Unary InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 6 cycles |