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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 04:07:58 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 04:07:58 +0000 |
| commit | 10dc63feeb7847f867a6f35179312f4079981ad3 (patch) | |
| tree | 7bf5a8373e146f6df2f5ab014ef6d3f87732b727 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | e90ea139f47752eb122af756a5714ef0b3756298 (diff) | |
Add VLD4 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 2d2bc370f5..06edaa9446 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -854,14 +854,36 @@ def CortexA9Itineraries : ProcessorItineraries< [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>, // // VLD4 - // FIXME: We don't model this instruction properly InstrItinData<IIC_VLD4, [InstrStage<1, [A9_DRegsN], 0, Required>, - // Extra latency cycles since wbck is 6 cycles - InstrStage<7, [A9_DRegsVFP], 0, Reserved>, + InstrStage<10, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_NPipe]>], - [2, 2, 2, 2, 1]>, + InstrStage<4, [A9_NPipe]>], + [4, 4, 5, 5, 1]>, + // + // VLD4ln + InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<11, [A9_DRegsVFP], 0, Reserved>, + InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<5, [A9_NPipe]>], + [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>, + // + // VLD4u + InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<10, [A9_DRegsVFP], 0, Reserved>, + InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<4, [A9_NPipe]>], + [4, 4, 5, 5, 2, 1]>, + // + // VLD4lnu + InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<11, [A9_DRegsVFP], 0, Reserved>, + InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<5, [A9_NPipe]>], + [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>, // // VST // FIXME: We don't model this instruction properly |