diff options
| author | David Goodwin <david_goodwin@apple.com> | 2009-08-11 22:38:43 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-08-11 22:38:43 +0000 |
| commit | 546952fd600ddba3f1eb6d4f93ff4eb42821a962 (patch) | |
| tree | 7b06ab7ec67d14a1bab1d9a63a36c71cb7d6cae7 /lib/Target/ARM/ARMSchedule.td | |
| parent | e28a2e8b70e926324575ddec0a1565c6dba7d404 (diff) | |
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index a5ca773ef1..11a7b2a717 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -10,8 +10,9 @@ //===----------------------------------------------------------------------===// // Functional units across ARM processors // -def FU_Pipe0 : FuncUnit; // pipeline 0 issue -def FU_Pipe1 : FuncUnit; // pipeline 1 issue +def FU_Issue : FuncUnit; // issue +def FU_Pipe0 : FuncUnit; // pipeline 0 +def FU_Pipe1 : FuncUnit; // pipeline 1 def FU_LdSt0 : FuncUnit; // pipeline 0 load/store def FU_LdSt1 : FuncUnit; // pipeline 1 load/store @@ -19,9 +20,11 @@ def FU_LdSt1 : FuncUnit; // pipeline 1 load/store // Instruction Itinerary classes used for ARM // def IIC_iALU : InstrItinClass; +def IIC_iMPY : InstrItinClass; def IIC_iLoad : InstrItinClass; def IIC_iStore : InstrItinClass; def IIC_fpALU : InstrItinClass; +def IIC_fpMPY : InstrItinClass; def IIC_fpLoad : InstrItinClass; def IIC_fpStore : InstrItinClass; def IIC_Br : InstrItinClass; @@ -31,12 +34,14 @@ def IIC_Br : InstrItinClass; def GenericItineraries : ProcessorItineraries<[ InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_iMPY , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, - InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]> + InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]> ]>; |