Add PredicateOperand to all ARM instructions that have the condition field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 77 insertions, 48 deletions

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 266f1b0567..890542aa1d 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -144,14 +144,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
         .addFrameIndex(FI).addImm(0);
     else
       BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
-          .addFrameIndex(FI).addReg(0).addImm(0);
+          .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL);
   } else if (RC == ARM::DPRRegisterClass) {
     BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
-    .addFrameIndex(FI).addImm(0);
+    .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
   } else {
     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
     BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
-      .addFrameIndex(FI).addImm(0);
+      .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
   }
 }
 
@@ -167,14 +167,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
         .addFrameIndex(FI).addImm(0);
     else
       BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
-      .addFrameIndex(FI).addReg(0).addImm(0);
+      .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL);
   } else if (RC == ARM::DPRRegisterClass) {
     BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
-      .addFrameIndex(FI).addImm(0);
+      .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
   } else {
     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
     BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
-      .addFrameIndex(FI).addImm(0);
+      .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
   }
 }
 
@@ -185,12 +185,17 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   if (RC == ARM::GPRRegisterClass) {
     MachineFunction &MF = *MBB.getParent();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-    BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr),
-            DestReg).addReg(SrcReg);
+    if (AFI->isThumbFunction())
+      BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
+    else
+      BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
+        .addImm((int64_t)ARMCC::AL);
   } else if (RC == ARM::SPRRegisterClass)
-    BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
+      .addImm((int64_t)ARMCC::AL);
   else if (RC == ARM::DPRRegisterClass)
-    BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg)
+      .addImm((int64_t)ARMCC::AL);
   else
     abort();
 }
@@ -199,7 +204,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
 /// specified immediate.
 static void emitLoadConstPool(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator &MBBI,
-                              unsigned DestReg, int Val, 
+                              unsigned DestReg, ARMCC::CondCodes Pred, int Val, 
                               const TargetInstrInfo &TII, bool isThumb) {
   MachineFunction &MF = *MBB.getParent();
   MachineConstantPool *ConstantPool = MF.getConstantPool();
@@ -209,7 +214,7 @@ static void emitLoadConstPool(MachineBasicBlock &MBB,
     BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
   else
     BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
-      .addReg(0).addImm(0);
+      .addReg(0).addImm(0).addImm((unsigned)Pred);
 }
 
 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
@@ -217,7 +222,9 @@ void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
                                     unsigned DestReg,
                                     const MachineInstr *Orig) const {
   if (Orig->getOpcode() == ARM::MOVi2pieces) {
-    emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(),
+    emitLoadConstPool(MBB, I, DestReg,
+                      (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
+                      Orig->getOperand(1).getImmedValue(),
                       TII, false);
     return;
   }
@@ -247,14 +254,15 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
   switch (Opc) {
   default: break;
   case ARM::MOVr: {
+    unsigned Pred = MI->getOperand(2).getImmedValue();
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
-        .addReg(0).addImm(0);
+        .addReg(0).addImm(0).addImm(Pred);
     } else {          // move -> load
       unsigned DstReg = MI->getOperand(0).getReg();
       NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
-        .addImm(0);
+        .addImm(0).addImm(Pred);
     }
     break;
   }
@@ -277,24 +285,28 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
     break;
   }
   case ARM::FCPYS: {
+    unsigned Pred = MI->getOperand(2).getImmedValue();
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
-        .addImm(0);
+        .addImm(0).addImm(Pred);
     } else {          // move -> load
       unsigned DstReg = MI->getOperand(0).getReg();
-      NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
+      NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
+        .addImm(0).addImm(Pred);
     }
     break;
   }
   case ARM::FCPYD: {
+    unsigned Pred = MI->getOperand(2).getImmedValue();
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
-        .addImm(0);
+        .addImm(0).addImm(Pred);
     } else {          // move -> load
       unsigned DstReg = MI->getOperand(0).getReg();
-      NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
+      NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
+        .addImm(0).addImm(Pred);
     }
     break;
   }
@@ -415,6 +427,7 @@ static
 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator &MBBI,
                              unsigned DestReg, unsigned BaseReg,
+                             ARMCC::CondCodes Pred,
                              int NumBytes, const TargetInstrInfo &TII) {
   bool isSub = NumBytes < 0;
   if (isSub) NumBytes = -NumBytes;
@@ -433,7 +446,8 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
     
     // Build the new ADD / SUB.
     BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
-      .addReg(BaseReg, false, false, true).addImm(SOImmVal);
+      .addReg(BaseReg, false, false, true).addImm(SOImmVal)
+      .addImm((unsigned)Pred);
     BaseReg = DestReg;
   }
 }
@@ -498,7 +512,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
       BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
         .addReg(LdReg, false, false, true);
     } else
-      emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true);
+      emitLoadConstPool(MBB, MBBI, LdReg, ARMCC::AL, NumBytes, TII, true);
 
     // Emit add / sub.
     int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@@ -618,11 +632,12 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
 
 static
 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
-                  int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
+                  ARMCC::CondCodes Pred, int NumBytes, bool isThumb,
+                  const TargetInstrInfo &TII) {
   if (isThumb)
     emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
   else
-    emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
+    emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, Pred, NumBytes, TII);
 }
 
 void ARMRegisterInfo::
@@ -643,11 +658,15 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       Amount = (Amount+Align-1)/Align*Align;
 
       // Replace the pseudo instruction with a new instruction...
-      if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
-        emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
+      unsigned Opc = Old->getOpcode();
+      bool isThumb = AFI->isThumbFunction();
+      ARMCC::CondCodes Pred = isThumb
+        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
+      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
+        emitSPUpdate(MBB, I, Pred, -Amount, isThumb, TII);
       } else {
-        assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
-        emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
+        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
+        emitSPUpdate(MBB, I, Pred, Amount, isThumb, TII);
       }
     }
   }
@@ -925,7 +944,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
         if (FrameReg == ARM::SP)
           emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
         else {
-          emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
+          emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true);
           UseRR = true;
         }
       } else
@@ -960,7 +979,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
         if (FrameReg == ARM::SP)
           emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
         else {
-          emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
+          emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true);
           UseRR = true;
         }
       } else
@@ -990,7 +1009,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     if (ScratchReg == 0)
       // No register is "free". Scavenge a register.
       ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
-    emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
+    MachineOperand *MO = MI.findFirstPredOperand();
+    ARMCC::CondCodes Pred = MO ?
+      (ARMCC::CondCodes)MO->getImmedValue() : ARMCC::AL;
+    emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred,
                             isSub ? -Offset : Offset, TII);
     MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
   }
@@ -1293,11 +1315,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
   int FramePtrSpillFI = 0;
 
   if (VARegSaveSize)
-    emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, -VARegSaveSize, isThumb, TII);
 
   if (!AFI->hasStackFrame()) {
     if (NumBytes != 0)
-      emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
+      emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII);
     return;
   }
 
@@ -1337,24 +1359,27 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   if (!isThumb) {
     // Build the new SUBri to adjust SP for integer callee-save spill area 1.
-    emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS1Size, isThumb, TII);
     movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
   } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
     ++MBBI;
 
   // Darwin ABI requires FP to point to the stack slot that contains the
   // previous FP.
-  if (STI.isTargetDarwin() || hasFP(MF))
-    BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
+  if (STI.isTargetDarwin() || hasFP(MF)) {
+    MachineInstrBuilder MIB =
+      BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
       .addFrameIndex(FramePtrSpillFI).addImm(0);
+    if (!isThumb) MIB.addImm(ARMCC::AL);
+  }
 
   if (!isThumb) {
     // Build the new SUBri to adjust SP for integer callee-save spill area 2.
-    emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS2Size, false, TII);
 
     // Build the new SUBri to adjust SP for FP callee-save spill area.
     movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
-    emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, -DPRCSSize, false, TII);
   }
 
   // Determine starting offsets of spill areas.
@@ -1371,7 +1396,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
     // Insert it after all the callee-save spills.
     if (!isThumb)
       movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
-    emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII);
   }
 
   if(STI.isTargetELF() && hasFP(MF)) {
@@ -1414,7 +1439,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
   int NumBytes = (int)MFI->getStackSize();
   if (!AFI->hasStackFrame()) {
     if (NumBytes != 0)
-      emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
+      emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII);
   } else {
     // Unwind MBBI to point to first LDR / FLDD.
     const unsigned *CSRegs = getCalleeSavedRegs();
@@ -1444,9 +1469,9 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
             &MBB.front() != MBBI &&
             prior(MBBI)->getOpcode() == ARM::tPOP) {
           MachineBasicBlock::iterator PMBBI = prior(MBBI);
-          emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
+          emitSPUpdate(MBB, PMBBI, ARMCC::AL, NumBytes, isThumb, TII);
         } else
-          emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
+          emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII);
       }
     } else {
       // Darwin ABI requires FP to point to the stack slot that contains the
@@ -1461,24 +1486,28 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
             hasFP(MF))
           if (NumBytes)
             BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
-              .addImm(NumBytes);
+              .addImm(NumBytes).addImm((unsigned)ARMCC::AL);
           else
-            BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr);
+            BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
+              .addImm((unsigned)ARMCC::AL);
       } else if (NumBytes) {
-        emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
+        emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, false, TII);
       }
 
       // Move SP to start of integer callee save spill area 2.
       movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
-      emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
+      emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getDPRCalleeSavedAreaSize(),
+                   false, TII);
 
       // Move SP to start of integer callee save spill area 1.
       movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
-      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
+      emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea2Size(),
+                   false, TII);
 
       // Move SP to SP upon entry to the function.
       movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
-      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
+      emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea1Size(),
+                   false, TII);
     }
   }
 
@@ -1488,7 +1517,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
       // FIXME: Verify this is still ok when R3 is no longer being reserved.
       BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
 
-    emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
+    emitSPUpdate(MBB, MBBI, ARMCC::AL, VARegSaveSize, isThumb, TII);
 
     if (isThumb) {
       BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);