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| author | Owen Anderson <resistor@mac.com> | 2011-03-29 17:42:25 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-03-29 17:42:25 +0000 |
| commit | 9eae80051b6f6f5564b725221b2163a1f0d83672 (patch) | |
| tree | 7f0b0edd71d3dc4933d1740680da8d0106c895d4 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | da6eed3cfea3a6468f3dc9076611438bf981256f (diff) | |
Add safety check that didn't show up in testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index af73116626..0dab835f7c 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -350,6 +350,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB, bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD); Opcode = getLoadStoreMultipleOpcode(Opcode, Mode); + if (!Opcode) return false; MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) .addReg(Base, getKillRegState(BaseKill)) .addImm(Pred).addReg(PredReg); |