diff options
| author | Cameron Zwarich <zwarich@apple.com> | 2011-05-18 21:25:14 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-05-18 21:25:14 +0000 |
| commit | 955db42568ae61c9f381a5af3e354d4270d06d92 (patch) | |
| tree | 6e4d3ab9910e13ef59b147a15c6a555db67e0df8 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 673968ae78f26bd78337d8bbb212fd280839fc12 (diff) | |
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index df89fadb31..8b9a82e276 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1672,10 +1672,14 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, Ops.pop_back(); Ops.pop_back(); + const TargetInstrDesc &TID = TII->get(NewOpc); + const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI); + MRI->constrainRegClass(EvenReg, TRC); + MRI->constrainRegClass(OddReg, TRC); + // Form the pair instruction. if (isLd) { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, - dl, TII->get(NewOpc)) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) .addReg(EvenReg, RegState::Define) .addReg(OddReg, RegState::Define) .addReg(BaseReg); @@ -1687,8 +1691,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, MIB.addImm(Offset).addImm(Pred).addReg(PredReg); ++NumLDRDFormed; } else { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, - dl, TII->get(NewOpc)) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) .addReg(EvenReg) .addReg(OddReg) .addReg(BaseReg); |