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author | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 18:08:01 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 18:08:01 +0000 |
commit | 13ab020ea08826f1b87db6ec3da63889a12e3d9d (patch) | |
tree | 37518534f9244509cc7188ef7b6b352a59690f5d /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
parent | 2bf821c4bfb945c71a86082472ce2f72d1b07473 (diff) |
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
-rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 4d773343ab..7562c5bf24 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -158,7 +158,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase) .addReg(Base, false, false, BaseKill).addImm(ImmedOffset) - .addImm(Pred).addReg(PredReg); + .addImm(Pred).addReg(PredReg).addReg(0); Base = NewBase; BaseKill = true; // New base is always killed right its use. } |