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authorEvan Cheng <evan.cheng@apple.com>2010-11-12 23:03:38 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-11-12 23:03:38 +0000
commit893d7fe2098cc81ba1b4ce0ed71f6f614843961f (patch)
tree335627272ec83d12ec49206fe935e07b23dc3927 /lib/Target/ARM/ARMInstrInfo.cpp
parentc0394c0b8cee513a624566ce1db100bd66d4da57 (diff)
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.cpp24
1 files changed, 0 insertions, 24 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index f6c2df2758..6f48d967f9 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -59,27 +59,3 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
return 0;
}
-
-void ARMInstrInfo::
-reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
- const TargetRegisterInfo &TRI) const {
- DebugLoc dl = Orig->getDebugLoc();
- unsigned Opcode = Orig->getOpcode();
- switch (Opcode) {
- default:
- break;
- case ARM::MOVi2pieces: {
- RI.emitLoadConstPool(MBB, I, dl,
- DestReg, SubIdx,
- Orig->getOperand(1).getImm(),
- ARMCC::AL, 0); // Pre-if-conversion, so default pred.
- MachineInstr *NewMI = prior(I);
- NewMI->getOperand(0).setSubReg(SubIdx);
- return;
- }
- }
-
- return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
-}
-