diff options
| author | Dale Johannesen <dalej@apple.com> | 2009-02-12 23:08:38 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2009-02-12 23:08:38 +0000 |
| commit | 21b5541814d57d0a31f353948e4e933dbb1af6a4 (patch) | |
| tree | 8f03d09512c1f2d3539b06262321b3b6ab0a0c54 /lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | c2390b14c91764cba6e4394d05e58e387a7dfb19 (diff) | |
Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 8578284a35..891d3a4a7e 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -555,13 +555,14 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -576,7 +577,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -614,12 +615,13 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR; - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -633,7 +635,7 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = ARM::FLDS; } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); |