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| author | Jim Grosbach <grosbach@apple.com> | 2010-08-11 15:44:15 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-08-11 15:44:15 +0000 |
| commit | fcba5e6b645df89ae6b93911fe0f80b08fa6b44c (patch) | |
| tree | 1fc917344b0ac16a11ad95e1b8f6b476fb7867f8 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | f63fed141ec2402a7f028498b07ca7d49113b61c (diff) | |
cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e4b556228f..073528abe8 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -266,7 +266,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) addRegisterClass(MVT::i32, ARM::GPRRegisterClass); if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { addRegisterClass(MVT::f32, ARM::SPRRegisterClass); - addRegisterClass(MVT::f64, ARM::DPRRegisterClass); + if (!Subtarget->isFPOnlySP()) + addRegisterClass(MVT::f64, ARM::DPRRegisterClass); setTruncStoreAction(MVT::f64, MVT::f32, Expand); } |